1. Field of the Invention
The present invention relates to a semiconductor integrated circuit designing method and program. More particularly, the present invention is concerned with a semiconductor integrated circuit designing method and program that implement automatic arrangement and connection according to a standard cell technique or the like.
2. Description of Related Art
FIG. 14A shows an example of a standard cell contained in a cell library A, and FIG. 14B shows an example of a standard cell contained in a cell library B. Hatched areas 121 in FIG. 14A and FIG. 14B indicate a first-layer Al line, and blank areas 122 therein indicate a second-layer Al line. FIG. 14A and FIG. 14B are identical to each other in terms of positions and names of terminals and outer dimensions of a cell. However, the Al layers used for electrodes or terminals in the cell shown in FIG. 14A are reverse to those in the cell shown in FIG. 14B. The cell libraries A and B are registered in a computer in advance. Cells to be arranged and interconnected in a block are selected from, for example, the library A. After the thus completed block is disposed, when the block is turned 90°, the library used to complete the block, or, the Al layer used for wiring is changed to the other one through computer-aided design (CAD). This process is much simpler than automatic connection. After the direction of the Al layer used for wiring is matched with the direction of Al layers in the other blocks, the blocks are interconnected.
As related arts, Japanese Unexamined Patent Application Publications Nos. 2-291148 and 2004-172594 have been disclosed.